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Features
* Minimal External Circuitry Requirements, no RF Components on the PC Board Except * * * * * * * * * * * *
Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates SSO20 and SO20 package Fully Integrated VCO Supply Voltage 4.5V to 5.5V, Operating Temperature Range -40C to +105C Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level Various Types of Protocols Supported (i.e., PWM, Manchester and Bi-phase) Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) ESD Protection According to MIL-STD. 883 (4KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front-end Filter, up to 40 dB is thereby Achievable with Newer SAWs Power Management (Polling) is Possible by Means of a Separate Pin via the Microcontroller Receiving Bandwidth BIF = 600 kHz
UHF ASK Receiver ATA5744
1. Description
The ATA5744 is a PLL receiver device for the receiving range of f0 = 300 MHz to 450 MHz. It is developed for the demands of RF low-cost data communication systems with low data rates and fits for most types of modulation schemes including Manchester, Bi-phase and most PWM protocols. Its main applications are in the areas of telemetering, security technology and keyless-entry systems.
Figure 1-1.
1 Li cell
System Block Diagram
UHF ASK/FSK Remote control transmitter UHF ASK Remote control receiver
U2741B Encoder ATARx9x
XTO
ATA5744
Demod. PLL
IF Amp
Data interface
1...3
Microcontroller
Keys
Antenna Antenna VCO PLL XTO
Power amp.
LNA
VCO
Rev. 4893A-RKE-11/05
2. Pin Configuration
Figure 2-1. Pinning SO20 and SSO20
ENABLE DVCC LFGND MODE DATA RSSI XTO LFVCC NC 10 11 TEST
19
20
18
16
15
14
13
17
ATA5744
8
2
4
6
1
3
BR_0
BR_1
AVCC
5
MIXVCC
AGND
7
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Description
Symbol BR_0 BR_1 CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC LFVCC LF LFGND XTO DVCC MODE RSSI TEST ENABLE DATA Function Baud rate select LSB Baud rate select MSB Lower cut-off frequency data filter Analog power supply Analog ground Digital ground Power supply mixer High-frequency ground LNA and mixer RF input Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator Digital power supply Selecting 433.92 MHz /315 MHz Low: 315 MHz (USA) High: 433.92 MHz (Europe) Output of the RSSI amplifier Test pin, during operation at GND Selecting operation mode Low: sleep mode High: receiving mode Data output
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LNAGND
LNA_IN
DGND
CDEM
9
12
LF
ATA5744
Figure 2-2. Block Diagram
BR_0 BR_1
CDEM
ASKDemodulator and data filter RSSI
Dem_out Data interface
DATA
RSSI AVCC
RSSI IF Amp
Test
TEST
AGND DGND 4. Order MODE DVCC ENABLE LFGND Standby logic LFVCC IF Amp
MIXVCC
LPF 3 MHz
LNAGND
LPF 3 MHz
VCO
XTO
XTO
f LNA_IN LNA 64 LF
3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to Figure 2-2, the front end consists of an LNA (Low-Noise Amplifier), LO (Local Oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (Voltage-Controlled Oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 3-1, the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered.
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Figure 3-1.
PLL Peripherals
VS DVCC CL XTO
LFGND
LF VS R1 C9 C10
R1 = 820 C9 = 4.7 nF C10 = 1 nF
LFVCC
The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: fLO = fRF - fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin mode. This is described by the following formulas: MODE = 0 USA fIF = fLO/314 MODE = 1 Europe fIF = fLO/432.92 The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where f RF = 315 MHz, MODE must be set to '0'. In the case of fRF = 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 on page 5 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver ATA5744 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network, is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network a mirror frequency suppression of PRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used.
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Figure 3-2 shows a typical input matching network for f RF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates the input matching to 50 without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the electrical characteristics.
Table 3-1.
Conditions
Calculation of LO and IF Frequency
Local Oscillator Frequency fLO = 314 MHz fLO = 432.92 MHz Intermediate Frequency fIF = 1 MHz fIF = 1 MHz
fRF = 315 MHz, MODE = 0 fRF = 433.92 MHz, MODE = 1
300 MHz < fRF < 365 MHz, MODE = 0
f RF f LO = ------------------1 1 + --------314 f RF f LO = --------------------------1 1 + ----------------432.92
f LO f IF = --------314
365 MHz < fRF < 450 MHz, MODE = 1
f LO f IF = ----------------432.92
Figure 3-2.
Input Matching Network with SAW Filter
ATA5744
8 LNAGND 8
ATA5744
LNAGND
C3 22p
L 25n
9
LNA_IN
C3 47p
L 25n
9
LNA_IN
C16
C17 8.2p
TOKO LL2012 F27NJ
C16
C17 22p
TOKO LL2012 F47NJ
100p
fRF = 433.92 MHz
L3 27n
100p
fRF = 315 MHz
L2 TOKO LL2012 F82NJ 1 C2 10p 82n 2 IN IN_GND
L3 47n
RFIN C2 8.2p
L2 TOKO LL2012 F33NJ 33n
1 2
IN
OUT OUT_GND IN_GND CASE_GND 3, 4 7, 8
B3555
5 6
RFIN
B3551
OUT
5 6
OUT_GND CASE_GND 3, 4 7, 8
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Figure 3-3.
Input Matching Network without SAW Filter
ATA5744 ATA5744
fRF = 433.92 MHz
8
LNAGND
fRF = 315 MHz
8
LNAGND
9 C3 15p 25n
LNA_IN
9 C3 33p 25n
LNA_IN
RFIN 3.3p 22n 100p TOKO LL2012 F22NJ
RFIN 3.3p 39n 100p TOKO LL2012 F39NJ
Please note that for all coupling conditions (see Figure 3-2 on page 5 and Figure 3-3), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB.
4. Analog Signal Processing
4.1 IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center frequency. The receiver ATA5744 employs an IF bandwidth of BIF = 600 kHz and can be used together with the U2741B in ASK mode.
4.2
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity.
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4.3 Pin RSSI
The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range PRef is -100 dBm to -55 dBm. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 3-3 and exhibits the best possible sensitivity. Figure 4-1. RSSI Characteristics
3.0 2.8 2.6 Tamb = 40C 2.4 2.2 2.0 1.8 1.6 min. 1.4 1.2 1.0 -130.0 105C 25C max.
VRRSI (V)
-110.0
-90.0
-70.0
-50.0
-30.0
PRef (dBm)
4.4
ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK demodulator. An automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 1st-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: 1 fcu_DF = ---------------------------------------------------2 x x R 1 x CDEM Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baudrate range (BR_Range). BR_Range is defined by the pins BR_0 and BR_1. BR_Range must be set in accordance to the used baudrate.
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Table 4-1.
Definition of BR_Range by the Pins BR_0 and BR_1
BR_1 0 0 1 1 BR_0 0 1 0 1 BR_Range 0 1 2 2
Each BR_Range is defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
4.5
Receiving Characteristics
The RF receiver ATA5744 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 4-1 on page 7. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA5744. Low-cost crystals are specified to be within 100 ppm. The XTO deviation of the ATA5744 is an additional deviation due to the XTO circuit. This deviation is specified to be 30 ppm. If a crystal of 100 ppm is used, the total deviation is 130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent. Figure 4-2. Receiving Frequency Response
0.0
without SAW
-20.0
dP (dB)
-40.0
-60.0
-80.0
with SAW
-100.0 -6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
df (MHz)
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4.6 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 4-3, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. According to chapter 'RF Front End', the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Figure 4-3. Generation of the Basic Clock Cycle
TClk MODE Divider :14/:10 fXTO 16 L : USA(:10) H: Europe(:14)
DVCC 15
XTO XTO 14
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following application-relevant parameters: Timing of the analog and digital signal processing IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter. * Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 s) * Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 s) * Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined by the pins BR_0 and BR_1. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 x TXClk = 4 x TXClk = 2 x TXClk = 1 x TClk TClk TClk TClk
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5. Pin ENABLE
Via the pin ENABLE the operating mode of the receiver can be selected (see Figure 5-1 and Figure 5-2). If the pin ENABLE is held to Low, the receiver remains in sleep mode. All circuits for signal processing are disabled and only the XTO is running in that case. The current consumption is IS = ISoff in that case. During the sleep mode the receiver is not sensitive to a transmitter signal. To activate the receiver, the pin ENABLE must be held to High. During the start-up period, TStartup, all signal processing circuits are enabled and settled. The duration of the start-up period depends on the selected baud-rate range (BR_Range). After the start-up period, all circuits are in a stable condition and the receiver is in the receiving mode. In receiving mode, the internal data signal (Dem_out) is switched to pin DATA. To avoid incorrect timing at the begin of the data stream, the begin is synchronized to a falling edge of the incoming data signal. The receiver stays in the receiving mode until it is switched back to sleep mode via pin ENABLE. During start-up and receiving mode, the current consumption is IS = ISon. Figure 5-1. Enable Timing (1)
Dem_out
ENABLE
tee_sig
DATA Sleep mode Start-up mode Receiving mode
I S = I Soff
I S = I Son TStart-up
I S = I Son
Figure 5-2.
Enable Timing (2)
Dem_out
ENABLE
tee_sig
DATA Sleep mode Start-up mode Receiving mode
I S = I Soff
I S = I Son TStart-up
I S = I Son
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6. Digital Signal Processing
The data from the ASK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal DATA. This processing depends on the selected baudrate range (BR_Range). Figure 6-1 on page 11 illustrates how Dem_out is synchronized by the extended basic clock cycle TXClk. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee_sig of the DATA signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee_sig TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller.
Figure 6-1.
Synchronization of the Demodulator Output
TXClk
Dem_out Data_out (DATA)
tee_sig
Figure 6-2.
Debouncing of the Demodulator Output
Dem_out DATA tDATA_min tDATA_min tDATA_min
tee
tee
tee
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7. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 Symbol VS Ptot Tj Tstg Tamb Pin_max -55 -40 Min. Max. 6 450 150 +125 +105 10 Unit V mW C C C dBm
8. Thermal Resistance
Parameters Junction ambient SO20 package Junction ambient SSO20 package Symbol RthJA RthJA Value 100 100 Unit K/W K/W
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9. Electrical Characteristics
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25C)
6.76438 MHz Osc. (MODE:1) Parameters Test Conditions Symbol Min. Typ. Max. 4.90625 MHz Osc. (MODE:0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit
Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk 2.0383 2.0697 16.6 8.3 4.1 2.1 1855 1061 1061 663 2.0697 16.6 8.3 4.1 2.1 1855 1061 1061 663 16.3 8.2 4.1 2.0 1827 1045 1045 653 16.3 8.2 4.1 2.0 1827 1045 1045 653 2.0383 1/(fxto/10) 1/(fxto/14) 8x 4x 2x 1x TClk TClk TClk TClk 1/(fxto/10) 1/(fxto/14) 8x 4x 2x 1x TClk TClk TClk TClk s s s s s s s s s s s
Extended basic clock cycle
TXClk
Start-up time (see Figure 5-1 and Figure 5-2 on page 10) Receiving Mode Intermediate frequency Minimum time period between edges at pin DATA
TStartup
896.5 512.5 512.5 320.5 x TClk
896.5 512.5 512.5 320.5 x TClk
MODE=0 (USA) MODE=1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 (Figure 6-2 on page 11) BR_Range0 BR_Range1 BR_Range2 BR_Range3 (Figure 5-1 on page 10)
fIF 165 83 41.4 20.7
1.0 1.0 165 83 41.4 20.7 163 81 40.7 20.4 163 81 40.7 20.4
fXTO x 64/314 fXTO x 64/432.92 10 x TXClk 10 x TXCl 10 x TXClk 10 x TXClk 10 x TXClk 10 x TXCl 10 x TXClk 10 x TXClk
MHz MHz s s s s
TDATA_min
Edge to edge time period of the data signal for full sensitivity
tee_sig
400 200 100 50
8479 8479 8479 8479
400 200 100 50
8350 8350 8350 8350
BR_Range x 2 s/TCLK
4097 x TCLK
s s s s
10. Electrical Characteristics (continued)
Parameters Current consumption LNA Mixer Third-order intercept point LNA/ mixer/ IF amplifier input matched according to Figure 3-3 on page 6 Input matched according to Figure 3-3 on page 6, required according to I-ETS 300220 Input matching according to Figure 3-3 on page 6 At 433.92 MHz At 315 MHz IIP3 -28 dBm Test Conditions Sleep mode (XTO active) IC active (startup-, receiving mode) pin DATA = H Symbol ISoff ISon Min. Typ. 190 7.1 Max. 276 8.7 Unit A mA
LO spurious emission at RFIn Noise figure LNA and mixer (DSB) LNA_IN input impedance
ISLORF NF ZiLNA_IN
-73
-57
dBm
7 1.0 || 1.56 1.3 || 1.0
dB k || pF k || pF
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10. Electrical Characteristics (continued)
Parameters 1 dB compression point (LNA, mixer, IF amplifier) Maximum input level Local Oscillator Operating frequency range VCO Phase noise VCO/LO Spurious of the VCO VCO gain For best LO noise (design parameter) R1 = 820 C9 = 4.7 nF C10 = 1 nF XTO crystal frequency, appropriate load capacitance must be connected to XTAL fXTAL = 6.764375 MHz (EU) fXTAL = 4.90625 MHz (US) Series resonance resistor of the crystal Static capacitance of the crystal Analog Signal Processing Input matched according to Figure 3-3 ASK (level of carrier) BER 10-3 (Manchester), fin = 433.92 MHz/ 315 MHz T = 25C, VS = 5V, fIF = 1 MHz BR_Range0 (1 kBd) BR_Range1 (2 kBd) BR_Range2 (4kBd) BR_Range3 (8 kBd) Sensitivity variation for the full operating range compared to Tamb = 25C, VS = 5V fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + PRef PRef +2.5 -1.5 dB fXTO = 6.764 MHz 4.906 MHz RS Co fosc = 432.92 MHz at 1 MHz at 10 MHz at fXTO KVCO fVCO L (fm) 299 449 MHz Test Conditions Input matched according to Figure 3-3 on page 6, referred to RFin Input matched according to Figure 3-3 on page 6, BER 10-3 Symbol IP1db Pin_max Min. Typ. -40 Max. Unit dBm
-20
dBm
-93 -113 -55 190
-90 -110 -47
dBC/Hz dBC/Hz dBC MHz/V
Loop bandwidth of the PLL
BLoop
100
kHz
Capacitive load at pin LF
CLF_tot
10
nF
XTO operating frequency
fXTO
6.764375 -30 ppm 4.90625 -30 ppm
6.764375 4.90625
6.764375 +30 ppm 4.90625 +30 ppm 150 220 6.5
MHz MHz pF
PRef_ASK
Input sensitivity
-107 -105 -103 -101
-110 -108 -106 -104
-112 -110 -108 -106
dBm dBm dBm dBm
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10. Electrical Characteristics (continued)
Parameters Sensitivity variation for full operating range including IF filter compared to Tamb = 25C, VS = 5V S/N ratio to suppress inband noise signals Dynamic range RSSI amplifier RSSI output voltage range RSSI gain RI of pin CDEM for cut-off frequency calculation 1 fcu_DF = ----------------------------------------------------2 x x R x CDEM 1 BR_Range0 BR_Range1 BR_Range2 BR_Range3 Upper cut-off frequency BR_Range0 BR_Range1 BR_Range2 BR_Range3 Test Conditions fin = 433.92 MHz/ 315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + PRef Symbol PRef Min. Typ. Max. Unit
+5.5 +7.5 10 60 1.0 20 28 40 33 18 10 6.8 1.75 3.5 7.0 14.0 2.2 4.4 8.8 17.6
-1.5 -1.5 12
dB dB dB dB
SNR RRSSI VRSSI GRSSI RI
3.0
V mV/dB
55
k nF nF nF nF
Recommended CDEM for best performance
CDEM
Upper cut-off frequency data filter
fu
2.65 5.3 10.6 21.2
kHz kHz kHz kHz
Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor ENABLE input - Low-level input voltage - High-level input voltage MODE input - Low-level input voltage - High-level input voltage BR_0 input - Low-level input voltage - High-level input voltage BR_1 input - Low-level input voltage - High-level input voltage TEST input - Low-level input voltage Test input must always be set to LOW VOI RPup VIl VIh VIl VIh VIl VIh VIl VIh VIl 0.08 50 0.3 65 0.2 x VS V k V V V V V V V V V
Iol = 1 mA Sleep mode Receiving mode Division factor = 10 Division factor = 14
39
0.8 x VS
0.8 x VS
0.2 x VS
0.8 x VS
0.2 x VS
0.8 x VS
0.2 x VS
0.2 x VS
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Figure 10-1. Application Circuit: fRF = 433.92 MHz, without SAW Filter
Vs
+ C7
C6 10 nF 10% 1 2 3 4 5 6 7 8 9 10 BR_0 BR_1 CDEM AVCC AGND DGND
ATA5744
C14 5% C13 10 nF 10% C3 15 pF 5% np0 39 nF DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC C12 150 pF C15 np0 10% 10 nF 10% 20 19 18 17 16 15 14 13 12 11 6.7643 MHz C11 12 pF 2% np0 DATA ENABLE RSSI
2.2 F 10% GND
MIXVCC LNAGND LNA_IN NC
Q1
C8 150 pF np0 10%
COAX
C17 3.3 pF 5% np0
C16 100 pF 5% np0 22 nH 5% R1
820 5% C9 4.7 nF 5% C10 1 nF 5%
L2
Figure 10-2. Application Circuit: fRF = 315 MHz, without SAW Filter
Vs
+ C7
C6 10 nF 10% 1 2 3 4 5 6 7 8 9 10 BR_0 BR_1 CDEM AVCC AGND DGND
ATA5744
C14 5% C13 10 nF 10% C3 33 pF 5% np0 39 nF DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC C12 150 pF C15 np0 10% 10 nF 10% 20 19 18 17 16 15 14 13 12 11 4.90625 MHz C11 15 pF 2% np0 DATA ENABLE RSSI
2.2 F 10% GND
MIXVCC LNAGND LNA_IN NC
Q1
C8 150 pF np0 10%
COAX
C17 3.3 pF 5% np0
C16 100 pF 5% np0 39 nH 5% R1
820 5% C9 4.7 nF 5% C10 1 nF 5%
L2
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Figure 10-3. Application Circuit: fRF = 433.92 MHz, with SAW Filter
Vs
+ C7
C6 10 nF 10% 1 2 3 4 5 6 7 8 9 10 C15 150 pF 10% np0 C16 100 pF 5% L3 np0 BR_0 BR_1 CDEM AVCC AGND DGND
ATA5744
C14 5% C13 10 nF 10% C3 22 pF 5% np0 39 nF DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC C12 C17 8.2 pF 5% np0 5 6 7 8 R1 820 5% C9 4.7 nF 5% C10 1 nF 5% 10 nF 10% 20 19 18 17 16 15 14 13 12 11 6.76438 MHz C11 Q1 12 pF 2% np0 DATA ENABLE RSSI
2.2 F 10% GND
MIXVCC LNAGND LNA_IN NC
C8 150 pF np0 10%
27 nH 5%
COAX
L2 C2 33 nH 5%
8.2 pF 5%
B3555 1 IN OUT 2 IN_GND OUT_GND 3 4 CASE_GND CASE_GND
Figure 10-4. Application Circuit: fRF = 315 MHz, with SAW Filter
Vs
+ C7
C6 10 nF 10% 1 2 3 4 5 6 7 8 9 10 C15 150 pF 10% np0 C16 100 pF 5% L3 np0 BR_0 BR_1 CDEM AVCC AGND DGND
ATA5744
C14 5% C13 10 nF 10% C3 47 pF 5% np0 39 nF DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC C12 C17 22 pF 5% np0 5 6 7 8 R1 820 5% C9 4.7 nF 5% C10 1 nF 5% 10 nF 10% 20 19 18 17 16 15 14 13 12 11 4.90625 MHz C11 Q1 15 pF 2% np0 DATA ENABLE RSSI
2.2 F 10% GND
MIXVCC LNAGND LNA_IN NC
C8 150 pF np0 10%
47 nH 5%
COAX
L2 C2 10 pF 5% 82 nH 5%
B3551 1 IN OUT 2 IN_GND OUT_GND 3 4 CASE_GND CASE_GND
17
4893A-RKE-11/05
11. Ordering Information
Extended Type Number ATA5744N-TKSY ATA5744N-TKQY ATA5744N-TGSY ATA5744N-TGQY Package SSO20 SSO20 SO20 SO20 Remarks Tube, Pb-free Taped and reeled, Pb-free Tube, Pb-free Taped and reeled, Pb-free
12. Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35 0.25 10.50 10.20 11
0.4 1.27 11.43 20
0.25 0.10
technical drawings according to DIN specifications
1
10
18
ATA5744
4893A-RKE-11/05
ATA5744
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
19
4893A-RKE-11/05
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4893A-RKE-11/05

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